Re: [cc65] macro arguments

From: Ullrich von Bassewitz <>
Date: 2004-05-11 22:41:44

On Sun, Apr 25, 2004 at 08:50:30PM +0200, Groepaz wrote:
> oh well..
>      ANC   Accu AND with memory, copy accu-bit 7 to carry
>      ARR   Accu AND with memory, ROR accu
>      ASR   Accu AND with memory, LSR accu
>      DCP   DEC memory, CMP memory
>      ISB   INC memory, SBC memory
>      LAX   LDA memory, TAX
>      NOP   No operation (various variants that take different amount of cycles)
>      RLA   ROL memory, AND accu, result into accu
>      RRA   ROR memory, ADC accu, result into accu
>      SAX   Accu AND with X-Register, result into memory
>      SBC   Subtract memory from accumulator with borrow (one byte version of sbc#$ff)
>      SBX   X-Register AND with accu, SBC memory, result into X-Register
>      SLO   ASL memory, ORA accu, result into accu
>      SRE   LSR memory, EOR accu, result into accu
> all stable (work on all known mask variants of the 6510) and all more or
> less useful.

There is now a new "6502X" cpu, that supports all official 6502 mnemonics plus
several illegal ones. I've used and
implemented the ones marked as "stable". Beware: Some of the opcodes differ
from your list.

The docs do contain an overview about the supported opcodes and its meaning.
There is no .Pxxx available, you will have to use

        .setcpu "6502X" 


The usual remark about feedback applies:-)



Ullrich von Bassewitz                        
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Received on Tue May 11 22:41:48 2004

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